The present invention generally relates to semiconductor integrated circuits, and more particularly, to the structure and formation of liner structures that create insulation and diffusion barriers for a metal conductor.
An integrated circuit (IC) generally includes a semiconductor substrate in which a number of device regions are formed by diffusion or ion implantation of suitable dopants. This substrate usually involves a passivating and an insulating layer required to form different device regions. The total thickness of these layers is usually less than one micron. Openings through these layers (called vias or contact holes) and trenches therein allow electrical contact to be made selectively to the underlying device regions. A conducting material such as copper is used to fill these holes, which then make contact to semiconductor devices.
The openings are typically lined with a liner material, i.e., a barrier layer, to prevent migration of the conducting material into the dielectric material, which can lead to electrical short circuits, rendering the circuit unusable. As the dimensions of semiconductor devices shrink in the quest to improve chip performance, proportional scaling of the interconnect dimensions is needed. However, the barrier layer in the feature sidewalls (both vias and trenches) maintains a required minimum thickness of 10 to 20 Angstroms. As a result, the volume fraction occupied by the liner layer in the interconnect structure dramatically increases and degrades the circuit performance, i.e., the cross-sectional area of the conductor is significantly reduced by the presence of the liner layer.